EnglishCancella i cookie per ripristinare le impostazioni di lingua associate al browser in uso
Titolo/Abstract/Parole chiave

Methodologies and Toolflows for the Predictable Design of Reliable and Low-Power NoCs

Ghiribaldi, Alberto (2014) Methodologies and Toolflows for the Predictable Design of Reliable and Low-Power NoCs. Tesi di Dottorato , Università degli Studi di Ferrara.

File PDF

Download (5MB) | Anteprima


    There is today the unmistakable need to evolve design methodologies and tool ows for Network-on-Chip based embedded systems. In particular, the quest for low-power requirements is nowadays a more-than-ever urgent dilemma. Modern circuits feature billion of transistors, and neither power management techniques nor batteries capacity are able to endure the increasingly higher integration capability of digital devices. Besides, power concerns come together with modern nanoscale silicon technology design issues. On one hand, system failure rates are expected to increase exponentially at every technology node when integrated circuit wear-out failure mechanisms are not compensated for. However, error detection and/or correction mechanisms have a non-negligible impact on the network power. On the other hand, to meet the stringent time-to-market deadlines, the design cycle of such a distributed and heterogeneous architecture must not be prolonged by unnecessary design iterations. Overall, there is a clear need to better discriminate reliability strategies and interconnect topology solutions upfront, by ranking designs based on power metric. In this thesis, we tackle this challenge by proposing power-aware design technologies. Finally, we take into account the most aggressive and disruptive methodology for embedded systems with ultra-low power constraints, by migrating NoC basic building blocks to asynchronous (or clockless) design style. We deal with this challenge delivering a standard cell design methodology and mainstream CAD tool ows, in this way partially relaxing the requirement of using asynchronous blocks only as hard macros.

    Tipologia del documento:Tesi di Dottorato (Tesi di Dottorato)
    Data:8 Aprile 2014
    Relatore:Bertozzi, Davide
    Coordinatore ciclo:Trillo, Stefano
    Istituzione:Università degli Studi di Ferrara
    Dottorato:XXVI Anno 2011 > SCIENZE DELL'INGEGNERIA
    Struttura:Dipartimento > Ingegneria
    Soggetti:Area 09 - Ingegneria industriale e dell'informazione > ING-INF/01 Elettronica
    Parole chiave:Network-on-Chip, Toolflows, Low-Power, Asynchronous, Fault-Tolerance
    Depositato il:08 Lug 2015 08:42


    Accesso riservatoAccesso riservato