ItalianoClear Cookie - decide language by browser settings



PDF File

Download (4MB) | Preview


    The semiconductor materials both in the form of heteropitaxial and homoepitaxial structures, offer huge potentialities due to a large variety of band energy structures which can be exploited in microelectronics (FET, HBTs) and optoeletronic (lasers, LEDs) devices. However, epitaxial integration of different semiconductors for device development present several issues regarding mainly the minimization of the defects within the heterostructures. To achieve this, materials with similar lattice constant should be used, so that the induced elastic strain in the overgrown film is minimized. Other than the physical constraints however, the choice of the high quality substrate must yield to a cost-effective solution to develop the devices. In the field of microelectronics, the silicon has remained the unparallel material of choice for complementary metal-oxide-semiconductor (CMOS) devices due to its large availability and relative low cost of the raw material. Born in the late 1950s and having since grown into an industry with annual revenues currently in excess of $200 bilion, the modern Si-based semiconductor microelectronics industry is an amazing technical and financial accomplishment. The continuous increase in devices performance requirements have highlighted the main limitation of the silicon device employment. The carrier mobility for both electrons and holes is relatively small respect to the III V alloys, which instead combine high electrical performance with equally high radiation interaction efficiency. Furthermore, the maximum velocity that these carriers can attain under high electric fields is also small, and this limits the cut off frequency of the Si-based microelectronic devices. Due to indirect bandgap also, light emission and absorption is fairly inefficient, making impractical its employment in optoelectronics devices. On the other hand, the higher physical and electrical properties of the III V alloys respect to silicon, are also coupled with relatively high costs. Furthermore, these compounds offer an high application flexibility as the relative composition of these alloys can be also tuned in order to obtain a specific optical or electrical properties. By employment of the Germanium however, the properties of the silicon can be enhanced drastically. SiGe compounds infact exhibit higher electron and hole mobility even if small relative Ge fraction is added to the silicon. Moreover, the application of strain engineering in microelectronic devices using strain-relaxed SiGe buffer layer have brought a drastic enhancement in electrical properties of silicon. These alloys offers in addition the possibility to integrate the high efficiency III V alloys with low cost silicon substrate. The generally large lattice mismatch between these materials and the silicon, give rise to several issue regarding epitaxy integration. High mismatched heterostructure infact, relax plastically the elastic strain by an uncontrollable process which lead to a high density of induced defects in the grown layers. Several methods have been developed to growth high quality Ge layers onto silicon substrate with only a small dislocation content, such as constant composition thin buffer layers, linearly graded buffer layer and terrace graded buffer layers. On the other hand, in case a pure Ge can be directly integrated into the silicon wafer, a subsequent overgrown of III V alloys can be performed generating a low density of induced dislocations. Also the technique employed for deposition play a determinant role on the final quality of the grown layer. Classical CVD techniques, are able to growth high quality epitaxial layers but suffers generally of a low growth rate. Furthermore, the high thermal budgets required for precursor cracking can lead to several defect generation processes which finally degrade the electrical properties of the grown layer. In this work, high quality pure Ge virtual substrate (VS) have been grown onto silicon substrate using the low energy plasma enhance chemical vapor deposition (LEPECVD) technique. The innovative epitaxial reactor have been developed at the Physics Department of the University of Ferrara in collaboration with Dichroic Cell, and have been installed in the clean room facilities. A very high growth rates, as high as 3 nm/s, can be obtain while maintaining an high crystallographic quality of the epilayers. Furthermore, the substrate temperature have been proved to play a determinant role on the epitaxial processes. Thus a numerical approach have been developed to assess the temperature profile during the epitaxial process within the LEPECVD reactor. The finite element analysis have highlighted several feature useful for the design improvement of the LEPECVD heating stage. Finally, pure Ge VS buffer layers have been obtain with a induced TDD as low as 105 cm-2. The low surface roughness and the high relaxation of the VS buffer layers obtained, put the basis for a cost-effective integration of the high efficient III-V alloys with Silicon substrates.

    Item Type:Thesis (PhD Thesis)
    Date:2 March 2012
    Tutor:Guidi, Vincenzo
    Coordinator:Guidi, Vincenzo
    Institution:Universita' degli studi di Ferrara
    PhD:XXIV Anno 2009 > FISICA
    Divisions:Dipartimento > Fisica
    Subjects:Area 02 - Scienze fisiche > FIS/01 Fisica sperimentale
    Uncontrolled Keywords:silicio, germanio, SiGe, LEPECVD
    Deposited on:13 Feb 2013 15:08


    View ItemView Item